Wafer Business

Wafer fabrication
without Wafer probing

Known Good Die Business

Wafer fabrication
including Wafer probing

Turnkey Business

Complete all fabrication

Design Service Flow

Design Service Flow

Step 01

Spec.Decision RTL Coding

Step 02


Step 03

Netlist Hand-off

Step 04

Netlis DFT Service

Design Service Level

Design Service 1
RTL Coding
Service 2
Service 3
Netlist Hand-Off
Service 4
DFT Service
Service 5
Placement Routing
Service 6
Verification & PG
Service 7
Test Vector Generation
Service 8
Failure Analysis
Level 0
Level 1
Level 2
Level 3
Level 0

Spec. Sign-off Model

Level 1

RTL-Sign-off Model

Level 2

Netlist Sign-off Model

Level 3

Layout-Sign-off Model

Main Design Service

RTL Check

- Linting & Optimization
- Test Design Rule Check
- Layout Guide

Design Review Organizer

- Design Methodology Review
- Pre-Layout Design Review
- Post-layout Design Review

Post Processing

- Double Via
- Pattern Generation
- Metal Slit

Synthesis for Timing Closure

- Synthesis for Power Optimization
- Static Timing Analysis
- Equivalence Check

Auto P&R

- Early Engagement
- PowerPlan/FloorPlan
- Chip Size Optimization
- P&R
- Timing Optimization

Full Custom Manual Layout

- Analog IC/IP
- Digital CMOS Logic
- Mixed Device
- Memory Device

Design For Testability

- Scan Design & ATPG
- Memory BIST/BIRA
- At-Speed Test Strategy

Verification & Post Processing

- Multi-Power LVS
- Physical Design Rule Check
- Noise Analysis
- IR-Drop/Rise Analysis
- Bonding Rule Check
- Antenna Rule
- Check

Our Strengths

Offering total integrated solutionoptimized for client's needs

GAONCHIPS, a specialist in ASIC development, has accomplished various projects, which involves planning, designing and developing the product. With the experience, GAONCHIPS has offered total integrated solution which can expand client's business to mass production. GAONCHIPS has solution for various industrial products as well as home appliances such as cell phone and TV.


Strategic cooperation with various FAB

Experience in 180nm ~ 7nm project

Experience in 180nm ~ 7nm project
IP Hardening : ARM Process, DDR PHY
Developing Huge product (150M Gates)
Low Power design project
A lot of ASIC / SOC development

Solution enabling Mass Production Capability

Supply Chain Management
Wafer Biz. as well as Turn-Key Biz

Total separation of intranet and internet for enhanced security

Limited access to FTP, Security Server (permission only to CEO, Team Leader, Security Manager)
24 hours monitoring by CCTV
24 hours FTP Server monitoring
Sealed USB and all output devices on Task Terminal PC