Technical Solution

SoC Solution
SoC Solution
RTL Design, Platform Design & Verification, FPGA Verification 부터
Design Service 분야의 DFT Insertion, Layout, PKG / Test까지
시스템반도체 개발 및 제작에 필요한 모든 솔루션을 제공합니다. 

Design Service Flow

  • STEP 1

    Spec. Decision
    RTL Coding

  • STEP 2

    Synthesis

  • STEP 3

    Netlist
    Hand-off

  • STEP 4

    DFT
    Service

  • STEP 5

    Placement
    Routing

  • STEP 6

    Verification
    & PG

  • STEP 7

    Test Vector
    Generation

  • STEP 8

    Failure
    Analysis

Design Service Level

Level SERVICE 1

Spec. Decision
RTL Coding

SERVICE 2

Synthesis

SERVICE 3

Netlist
Hand-off

SERVICE 4

DFT
Service

SERVICE 5

Placement
Routing

SERVICE 6

Verification
& PG

SERVICE 7

Test Vector
Generation

SERVICE 8

Failure
Analysis

Level 0

Spec. Sign-off Model

Level 1

RTL Sign-off Model

Level 2

Netlist Sign-off Model

Level 3

Layout Sign-off Model

Total Solution

  • FULL CHIP DESIGN

    ( SPEC / DESIGN )

    Design / Verification Platform

    System Architecture Analysis

    Power Management Control

    Real Emulation with FPGA

    IP Supplier Partnership

  • PHYSICAL
    IMPLEMENTATION

    ( SYNTHESIS / DFT )

    DFT (SCAN / BIST / JTAG)

    STA (Static Timing Analysis)

    Synthesis & Timing Closure

  • PHYSICAL DESIGN

    ( AUTO P&R )

    Hierarchical Physical Design

    Low Power Design

    Flip Chip Physical Design

    Power & Signal Integrity

    Physical Verification

  • PKG & TEST Develop

    ( Assembly & TEST )

    Package Design

    Test vector generation

    ATE test set-up

    Qualification & Reliability

    Q.A & Failure analysis

  • Mass Production

    ( SCM )

    Wafer Business

    Full Turn-key Business
    (Wafer + PKG + TEST)

Advanced Technology

  • Mobile & Communication
    Mobile AP, 5G Modem,
    V2X communication network
  • IoT
    Smart Home, Audio processor, Wi-Fi, RF SoC,
    Printer SoC, Wearable
  • Automotive
    ADAS, Cluster, Cockpit, In / Outside Camera,
    Dash-board Camera(DVR)
  • Display
    Touch, Timing Controller, RGB / IR Sensor ISP,
    Video Scaler, UHD TV SoC
  • AI
    Server AI, NPU, AR Controller,
    Micro AI
  • Security
    Digital Security SoC, ISP for CCTV camera,
    Block Chain, Set-top box
SoC Design
가온칩스는 PPA(Power, Performance, Area) 최적화, 비용 절감,
개발 일정 단축을 효과적으로 지원하는 SoC 설계 솔루션을 제공합니다.

Vision & Mission

Customized
SoC Design Solution
Provider

  • 01

    SoC Design Solution

    Spec-to-Desgin

    SoC System Desgin

    SoC Verification

    SoC FPGA protype

    Reliable Design Process

  • 02

    SoC Design Platform

    SoC System Platform

    SoC Verification Platform

    SoC FPGA Platform

    ARM Partnership

    IP Supplier Partnership

    Early Start, Fast Optimize

  • 03

    High-Performance Design

    NoC / Memory System Optimization

    Maximize Clock Frequency

    Hardening for Computing Clusters

    Physical Design Consideration

  • 04

    Low-Power Design

    Power Domain Scenario

    Design for Dynamic clock-gating

SoC Design Solution

  • 01

    SoC Design

    System Architecture

    Processing Core

    NoC/Memory System

    External High-speed Interface

    Micro Architecture

  • 02

    SoC Verification

    Bus Functional Modeling

    Module/System Level in a Unified Testbench

    UVM methodology with VIP

    Bus Traffic Modeling & Performance Verification

  • 03

    SoC FPGA prototype

    FPGA Board Design

    Connected multiple FPGA targeting

    Verification with Firmware

SoC Design Platform

SoC System Platform

ARM-based SoC System : Ready for Entry-to-Cutting Edge

3rd Party IP with Partnership

Early Start and Fast Optimization

SoC Verification Platform

Systematic Configured & Re-usable Environment

All Verification Cases from Top to Sub in One Environment

Configurable Alternative Models for Integrated Units

Light and Reliable against Integration Issue

Easy Porting your System into One Verification Env.

SoC FPGA Platform

FPGA board with SoC System Platform

Fast Emulation for your IP on SoC System Platform

Fast Emulation for your System

Fast Iteration for your IP/System Architecture

High Performance

Physical
Implementation

Hardening for
Computing Clusters

CPU

GPU

NPU

Hash Core

Physical & Power-aware
Logic Synthesis

Logic Synthesis with physical information and power scenario

Placement-Aware Multi-Bit Register Banking

Physically aware Clock Gating restructuring

Design For Testability

Support advanced DFT solutions Low pin count test with serializer Power Aware DFT Test Fail Diagnosis

Logic / Memory BIST (Built in Self Test) In-System test method against progressive faults in logic area Fault injection simulation for safety analysis of design Shared Bus BIST/BIRA/BISR

SCAN (Advanced DFT Skill) Scan test for improved test coverage for lower DPPM Stuck-At, Bridge, Transition, Path-delay, OCCT, Burn-in

IDDQ Test IDDQ test for additional fault coverage

Boundary Scan Inter-chip connection test method for system level testing

Physical DFT consider Physical Reordering and Repartitioning

Physical Design

Accurate and
robust timing analysis

LVF based variability library

Moment-based LVF to cope with non-Gaussian effect

Parametric OCV method

CCS/CCSN-based STA

Statistical Rvia STA

NP-Skewed corner STA for hold timing, min-pulse, and DCD check only

Physical optimization

BEOL-aware delay optimization (BEOL resistance increase impacting path delay)

Mixed DDB/MDB Flow

Physical-aware Timing ECO

Minimize physical side-effect for ECO

MIM-aware Timing ECO

Produce a single ECO file for Multiply Instantiated Module

Accelerate multi-core CPU/GPU timing closure

Low Power
  • 01

    Dynamic Power Optimization

    Multi-supply Voltage & Voltage Island

    In-Rush Current prevented power gating

    Clock/Memory-Gating

    Dynamic Voltage Frequency Scaling

    Vector-Driven Optimization

    Decap pre-placement method

    Merge or split ICG / Multi-bit flip-flop

    Low Power CTS (Concurrent Clock and
    Data Optimization)

  • 02

    Leakage Power Optimization

    Multi-Vth Optimization

    Gate-Length Biasing

    Sign-off Leakage Optimization

  • 03

    Low Power Verification

    Low power static rule check

    Power-aware Simulation

    Power-aware equivalence check

Power & Signal Integrity
  • 01

    Power Integrity Solution

    Power Plan based on Early Prototyping Analysis

    Dynamic Voltage Drop Analysis

    Static Power Analysis

    Power EM / BUMP Current

    P/G Resistance check

  • 02

    Signal Integrity Solution

    Signal EM

    Glitch Noise analysis

    Clock Jitter validation

    Duty-cycle distortion methodology

    Clock Propagation Check

    3-row decap inverter on CTS